Design-for-Test Approaches in Scalable and High-Performance NoC Architectures: Challenges and Solutions

Abstract

The high rate of development of semiconductor technologies has led to the current predominance of NoC as an interconnect paradigm in System-on-Chip (SoC) devices, where it has a higher scalability, performance, and power consumption than bus or crossbar-based designs. By facilitating router-based packet switching, supporting globally asynchronous locally synchronous (GALS) systems and integrating the power of efficient routing strategies, NoCs have moved to the forefront in overcoming the escalating complexity of multi-core/many-core systems. These architectures are however, challenged by the shrinking technological nodes the size of transistors embedded in the computer chip), process variations, run-time errors and structural defects that can cause packet corruption, out-of-sync communication, or even outright system failure. Reliability has required fault resiliency and fault robust error checking structures. Design-for-Test (DFT) methodologies are therefore central in this scenario, offering systematic fault detection, diagnosis and tolerance approaches and PPA trade-offs. DFT improves performance and lowers test expense in addition to guaranteeing time-to-market productivity on a variety of high-performance computing (HPC), graphics processing units (GPUs), artificial intelligence (AI) accelerators, and data center processors. Moreover, as more sophisticated integration methods, namely 2D/3D stacking, heterogeneous systems and adaptive routing protocols, get adopted, testability has become a key design consideration that has an impact on overall system reliability. The paper discusses the symbiosis between NoC design and DFT, identify emerging challenges, architectural implementation, and approaches needed in designing scalable, fault tolerant and high-performance NoC-based systems.